In order to reduce cost of electronic equipments and/or reduce design cycle time, manufacturers design as much functionality on to a chip as possible. For example, the chip may comprise a processor, memory, and most of the circuitry required for a particular application, for example, digital signal processing for a cell phone. Some additional off-chip circuitry, for example, radio frequency (RF) circuitry to receive and transmit RF signals, may be required. Systems designed with these chips may generally be referred to as system-on-chip (SoC) designs.
Although SoC designs may comprise on-chip memory, for example, random access memory (RAM), more memory may be required than is available on the chip. Accordingly, there may be a caching system to access the off-chip memory. The caching system may comprise two levels of caches—level 1 (L1) and level 2 (L2). L2 cache may contain a subset of information in the off-chip main memory and L1 cache may contain a subset of information in the L2 cache. These may be considered to be examples of “inclusion property” where the main memory includes information in the L2 cache, and the L2 cache includes information in the L1 cache. In this regard, the inclusive L2 cache may have data in the L1 cache. When a processor requires data that is not in the L1 cache, the processor will attempt to fetch a copy of the data from the L2 cache. When the L2 cache receives a processor data request, it will provide a copy if it has a most recent copy of the requested data. Otherwise, the data will be fetched from the main memory.
However, there may be problems when a SoC embeds a symmetric multi-processing (SMP) system with, for example, four processors. Each of the four processors may have a L1 cache, and the four L1 caches may be supported by a unified L2 cache. When a processor needs data that is not in its L1 cache, a search may be made of the other L1 caches. Therefore, there may be duplicate data in various L1 caches when more than one processor needs the same data. Additionally, a classic problem of an SMP system is how to maintain cache coherence. Since each of the four L1 caches may keep a copy of a particular data, when a processor modifies its local copy, it may lead to data inconsistency with other copies in the other three L1 caches and the L2 cache.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.